1. Field
Various embodiments relate to a semiconductor design technology, and more particularly, to a semiconductor memory device, a test control system, and a method of operating a test control system.
2. Description of the Related Art
Semiconductor memory devices are generally divided into two types of memory devices, volatile memory devices and non-volatile memory devices. Examples of volatile memory devices include, but are not limited to, a Dynamic Random Access Memory (DRAM) device, and a Static Random Access Memory (SRAM) device. Examples of non-volatile memory devices include, but are not limited to, a Programmable Read Only Memory (PROM) device, an Erasable PROM (EPROM), an Electrically EPROM (EEPROM), and a flash memory device. A volatile memory device can be distinguished from a non-volatile memory device based on whether the data stored in the memory cells are retained when power supply is cut off. The volatile memory device does not retain the data stored in the volatile memory device memory cells when power supply is cut off, whereas the non-volatile memory device retains the data stored in the non-volatile memory device memory cells when the power supply is cut off. Volatile memory devices typically include additional circuitry for retaining the data stored in its memory cells.
Increases in the degree of integration of the semiconductor memory devices has resulted in decreases in the size of the memory bank. Decreases in the size of the memory bank has led to relatively shorter distances between word lines coupled to adjacent memory cells. Referring to FIG. 1 a circuit diagram representation of a section of an example of a prior art flash memory device is shown.
The semiconductor memory device includes a plurality of memory cells 110 for storing data. The plurality of memory cells 110 are electrically coupled in series between a bit line BL and a source line SL. A drain selection transistor DST is electrically coupled between the plurality of memory cells 110 and the bit line BL, and electrically couples the plurality of memory cells 110 with the bit line BL in response to a signal received via a drain selection line DSL. A source selection transistor SST is electrically coupled between the plurality of memory cells 110 and the source line SL, and electrically couples the plurality of memory cells 110 with the source line SL in response to a signal received via a source selection line SSL. Each of the plurality of memory cells 110 is electrically coupled to a corresponding one of a plurality word lines WL1-WLn, where n is a nature number. The plurality word lines WL1-WLn are used to read data from and write data to the plurality of memory cells and are driven to predetermined voltage levels during the performance of a write operation or a read operation.
As the distance between adjacent word lines decreases with advances in technology, a word line may improperly electrically couple to an adjacent word line and impact the performance of the memory cells that are electrically coupled to such word lines.